The present invention generally relates to testing methods, testing circuits and semiconductor integrated circuits having a testing circuit, and more particularly to a testing method, a testing circuit and a semiconductor integrated circuit having the testing circuit for testing blocks of the semiconductor integrated circuit.
Recently, there are demands to develop a standard-cell LSI in which blocks having the functions of the conventional LSI chips are integrated, so as to provide systems such as computers on chips. Similarly to the conventional system design in which the LSI is often treated as a black box, the block is often treated as a black box when the user makes the circuit design of the standard-cell LSI. For this reason, the manufacturer of the standard-cell LSI must test each of the blocks to guarantee the functions of the blocks. However, it is difficult to make direct access to the blocks from the external signal pins of the LSI because the number of signal pins on the LSI is limited. Hence, there is a demand to provide a means within the LSI that would enable testing of each block.
In the conventional LSI chip, when testing a part of the LSI to which a direct access cannot be made from the external signal pin of the LSI, flip-flops or the like are used to read and write the test data.
When using the flip-flops to test each block, the flip-flops are connected to input and output terminals of each block, for example. The flip-flops connected to the input terminals are used for writing the test data, and the flip-flops connected to the output terminals are used for reading the test data.
As methods of writing and reading the test data, there basically are two methods. According to a first method, scan-in and scan-out functions are provided in each latch circuit and the test data is selectively written and read out based on the scan address. On the other hand, according to a second method, a shift register is formed by connecting the flip-flops in series and the test data is written and read out by a shift operation of the shift register.
According to the conventional testing method, the latch circuits or flip-flops are provided at the input and output terminals of each block. By the provision of the latch circuits or flip-flops, the scale of the circuit of each block becomes large. As a result, there are problems in that the area occupied by each block increases, the power consumption of each block increases, the propagation delay time increases and the like, thereby deteriorating the performance of the LSI.
Furthermore, when the first method described above is employed to write and read out the test data, it is necessary to connect address and clock signal lines to each latch circuit, and the number of interconnections which must be connected to each block increases. That is, there is a need to widen the channel region for the interconnections between the blocks, and this leads to a further decrease in the integration density.
FIG. 1 schematically shows the interconnections between the blocks when the first method is employed. In FIG. 1, a semiconductor integrated circuit includes a block 100.sub.i having an input part 101.sub.i and an output part 102.sub.i, where i=1, 2 and 3 in this case. A group of interconnections made up of an address line, a clock signal line and the like for the latch circuits forms a test bus 104. As may be seen from FIG. 1, the test bus 104 is connected to both the input part 101.sub.i and the output part 102.sub.i of each block 100.sub.i and the number of interconnections is extremely large. FIG. 1 also shows an input terminal group 106 and an output terminal group 107.
On the other hand, when the second method described above is employed to write and read out the test data, it takes a long time to write and read out the test data as the number of flip-flops becomes large. As a result, the test time becomes long and the efficiency of the test process becomes poor.